1. Field of the Invention
The present invention relates to a hardware control method in an instruction control apparatus having an instruction processing suspension unit and a hardware error detection unit.
2. Description of the Related Art
In order to improve the reliability of an instruction control apparatus, there exists an instruction control apparatus which is provided with an error detection unit for monitoring the state of the hardware constituting the instruction control apparatus. Hardware errors were classified into errors which can be deterred and errors which cannot be deterred, as shown in FIG. 1.
Errors which can be deterred mean the errors for which processing does not need to be suspended immediately to perform error processing such as a correctable error of cache memory (when the cache memory is protected by ECC, errors can be automatically corrected up to a specific number of bits) because the errors do not directly affect instruction processing. There exists a technology which deters the detection of such an error by an error detection deterring unit, or temporarily reserves a report of an error detected by an error report deterring unit.
Errors which cannot be deterred mean the errors for which processing needs to be immediately suspended to perform error processing such as an error of a program counter because said errors directly affect instruction processing. If the detection of such an error is deterred, there is a possibility that a serious situation such as garbled data in which a program runs out of control and destroys data occurs, so that no error detection deterring unit is provided in the error detecting unit of the hardware such as a program counter.
Then, when an error occurs, it is judged whether the error is the one which cannot be deterred, and if it is the error which cannot be deterred, the error is detected, and if it is not the error which cannot be deterred, the error is detected or not detected according to the conditions of whether the detection of the error is deterred or not, as shown in FIG. 2.
By the way, when an error which cannot be deterred is detected, the error sometimes gets back to the state where normal processing can be performed for it again by subsequent error processing, but normal processing cannot be sometimes carried on. For example, when an error occurs to a program counter, even if it is an intermittent error, its restoration based on error processing is impossible because correct values of the program counter are unknown, and normal processing cannot be carried on.
Therefore, when the error is an intermittent error, there is a possibility that normal processing can be carried on if the scope in which the error which cannot be deterred is produced can be made narrow, and as a result, the reliability of the apparatus is also raised.
There has existed an instruction processing apparatus having the unit for temporarily suspending instruction processing. Also, a multi-threading processor which processes a plurality of instruction streams has been proposed lately, and in order to switch and execute a plurality of instruction streams, the instruction processing of the instruction streams which are being executed is temporarily suspended. In such an instruction processing apparatus, improvement of its reliability is required, and so it is desirable to narrow the scope in which an error which cannot be deterred among errors occurring to the hardware is produced.
However, when a hardware error occurs in the instruction execution unit of an information processing apparatus, even if it is a software error due to alpha rays and the hardware becomes temporarily abnormal, error detection used to be conducted without fail, as described in Patent Document 1 below.
Patent Document 1: Japanese Published patent application No. 7-219794